The synthesis of register transfer level (RTL) based design is a process of translating hardware descriptive language (HDL) coded design to required technology logic gates based on library technology provided and given timing constraints. In order for a design to be synthesized to the required technology logic gates, timing constraints are normally imposed from the top level onto the input and output pins. Based on the timing constraints of the input and output pins, the logic gates are inferred based on the HDL-coded design to meet these timing constraints. This achieves the required speed of operation and logic functionality using the logic gate library technology provided.
However, current designs are increasingly complex and larger, and incorporate more functionality into a smaller piece of silicon. The approach of synthesizing designs using top-level synthesis by imposing the timing constraints of input and output pins creates a bottleneck in achieving a fast turn-around time for achieving a required speed of operation and logic functionality to satisfy the demanding fast time-to-market environment of integrated circuit innovations.